regex101: Python Match Workspace

Regular Expression

(?:\A|\n{2})PASS:.*(?:\nPASS:.*)*\n(?!FAIL:).*CLPM_FPGA_(\d+)

New

PASS: PLL Lock signal state at reset is 0.
PASS: PLL Lock signal state is 1.
PASS: PLL Locked within expected time: 5000000 ps.
Requirements verified: CLPM_FPGA_31

PASS: System Clock high period is 8000 ps.
FAIL: System Clock low period is 8000 ps.
PASS: System Clock period is 16000 ps.
Requirements verified: CLPM_FPGA_32

PASS: System Clock to IFC delay is 10 ps.
Requirements verified: CLPM_FPGA_33

PASS: System Clock to IFC delay is 10 ps.
Requirements verified: CLPM_FPGA_34

FAIL: System Clock low period is 8000 ps.
PASS: System Clock high period is 8000 ps.
PASS: System Clock period is 16000 ps.
Requirements verified: CLPM_FPGA_35

PASS: System Clock high period is 8000 ps.
PASS: System Clock period is 16000 ps.
FAIL: System Clock low period is 8000 ps.
Requirements verified: CLPM_FPGA_36

FAIL: System Clock low period is 8000 ps.
Requirements verified: CLPM_FPGA_37

PASS: System Clock to IFC delay is 10 ps.
FAIL: System Clock low period is 8000 ps.
Requirements verified: CLPM_FPGA_38

PASS: System Clock to IFC delay is 10 ps.
Requirements verified: CLPM_FPGA_39

Substitution

PASS: PLL Lock signal state at reset is 0.
PASS: PLL Lock signal state is 1.
PASS: PLL Locked within expected time: 5000000 ps.
Requirements verified: CLPM_FPGA_31

PASS: System Clock high period is 8000 ps.
FAIL: System Clock low period is 8000 ps.
PASS: System Clock period is 16000 ps.
Requirements verified: CLPM_FPGA_32

PASS: System Clock to IFC delay is 10 ps.
Requirements verified: CLPM_FPGA_33

PASS: System Clock to IFC delay is 10 ps.
Requirements verified: CLPM_FPGA_34

FAIL: System Clock low period is 8000 ps.
PASS: System Clock high period is 8000 ps.
PASS: System Clock period is 16000 ps.
Requirements verified: CLPM_FPGA_35

PASS: System Clock high period is 8000 ps.
PASS: System Clock period is 16000 ps.
FAIL: System Clock low period is 8000 ps.
Requirements verified: CLPM_FPGA_36

FAIL: System Clock low period is 8000 ps.
Requirements verified: CLPM_FPGA_37

PASS: System Clock to IFC delay is 10 ps.
FAIL: System Clock low period is 8000 ps.
Requirements verified: CLPM_FPGA_38

PASS: System Clock to IFC delay is 10 ps.
Requirements verified: CLPM_FPGA_39