use strict;
my $str = 'PASS: PLL Lock signal state at reset is 0.
PASS: PLL Lock signal state is 1.
PASS: PLL Locked within expected time: 5000000 ps.
Requirements verified: CLPM_FPGA_31
PASS: System Clock high period is 8000 ps.
FAIL: System Clock low period is 8000 ps.
PASS: System Clock period is 16000 ps.
Requirements verified: CLPM_FPGA_32
PASS: System Clock to IFC delay is 10 ps.
Requirements verified: CLPM_FPGA_33
PASS: System Clock to IFC delay is 10 ps.
Requirements verified: CLPM_FPGA_34
FAIL: System Clock low period is 8000 ps.
PASS: System Clock high period is 8000 ps.
PASS: System Clock period is 16000 ps.
Requirements verified: CLPM_FPGA_35
PASS: System Clock high period is 8000 ps.
PASS: System Clock period is 16000 ps.
FAIL: System Clock low period is 8000 ps.
Requirements verified: CLPM_FPGA_36
FAIL: System Clock low period is 8000 ps.
Requirements verified: CLPM_FPGA_37
PASS: System Clock to IFC delay is 10 ps.
FAIL: System Clock low period is 8000 ps.
Requirements verified: CLPM_FPGA_39
PASS: System Clock to IFC delay is 10 ps.
Requirements verified: CLPM_FPGA_40';
my $regex = qr/(?:(?<=^)|(?<=\n{2}))PASS.+?(?!FAIL).+?CLPM_FPGA_(\d{2})/isp;
if ( $str =~ /$regex/g ) {
print "Whole match is ${^MATCH} and its start/end positions can be obtained via \$-[0] and \$+[0]\n";
# print "Capture Group 1 is $1 and its start/end positions can be obtained via \$-[1] and \$+[1]\n";
# print "Capture Group 2 is $2 ... and so on\n";
}
# ${^POSTMATCH} and ${^PREMATCH} are also available with the use of '/p'
# Named capture groups can be called via $+{name}
Please keep in mind that these code samples are automatically generated and are not guaranteed to work. If you find any syntax errors, feel free to submit a bug report. For a full regex reference for Perl, please visit: http://perldoc.perl.org/perlre.html