import re
regex = re.compile(r"^Compile success [0-9]+ Errors [0-9]+ Warnings Analysis time : [0-9]+\.[0-9]+ \[ms\]", flags=re.MULTILINE)
test_str = ("VHDL/Verilog/EDIF/SystemC Simulator build 10.3.3558.6081 \n\n"
"(c) 1997-2016 Aldec, Inc. All rights reserved.\n\n"
"License Number 0\n\n"
" Welcome to VSIMSA!\n"
" This message was printed from `startup.do' macro file.\n\n"
"# creating library\n"
"alib work\n"
"ALIB: Library `work' attached.\n\n"
"Compile success 0 Errors 0 Warnings Analysis time : 31.0 [ms]\n"
"Compile Package \"BT601_cfg\"\n"
"Compile success 0 Errors 0 Warnings Analysis time : 15.0 [ms]\n"
"# starting simulation with tb_top as the top level module\n"
"# asim fpc_tb\n"
"# running the simulation\n"
"# run 1000us\n"
"echo hi\n"
"hi\n"
"quit")
matches = regex.finditer(test_str)
for match_num, match in enumerate(matches, start=1):
print(f"Match {match_num} was found at {match.start()}-{match.end()}: {match.group()}")
for group_num, group in enumerate(match.groups(), start=1):
print(f"Group {group_num} found at {match.start(group_num)}-{match.end(group_num)}: {group}")
Please keep in mind that these code samples are automatically generated and are not guaranteed to work. If you find any syntax errors, feel free to submit a bug report. For a full regex reference for Python, please visit: https://docs.python.org/3/library/re.html