re = /^Compile success [0-9]+ Errors [0-9]+ Warnings Analysis time : [0-9]+\.[0-9]+ \[ms\]/m
str = 'VHDL/Verilog/EDIF/SystemC Simulator build 10.3.3558.6081
(c) 1997-2016 Aldec, Inc. All rights reserved.
License Number 0
Welcome to VSIMSA!
This message was printed from `startup.do\' macro file.
# creating library
alib work
ALIB: Library `work\' attached.
Compile success 0 Errors 0 Warnings Analysis time : 31.0 [ms]
Compile Package "BT601_cfg"
Compile success 0 Errors 0 Warnings Analysis time : 15.0 [ms]
# starting simulation with tb_top as the top level module
# asim fpc_tb
# running the simulation
# run 1000us
echo hi
hi
quit'
# Print the match result
str.scan(re) do |match|
puts match.to_s
end
Please keep in mind that these code samples are automatically generated and are not guaranteed to work. If you find any syntax errors, feel free to submit a bug report. For a full regex reference for Ruby, please visit: http://ruby-doc.org/core-2.2.0/Regexp.html